The present invention relates to data transfer between phase independent clock domains and, more particularly, but not exclusively to a method or apparatus for deterministic data transfer between commonly clocked domains wherein an exact or variable phase difference is introduced by such factors as the circuit geometry.
The trend today in silicon chip design is towards VLSI, and with larger and larger chips, smaller and smaller features and higher and higher clock rates, the result is that different regions on the chip can no longer be relied upon to be in time with a common clock. Even if the entire chip is commonly clocked, phase differences at different areas of the chip mean that interactions such as data transfer between one area and the other may require additional synchronization.
More specifically, in the current art, the transfer of data between two logic sections located at relatively large distance from each other, typically entails the utilization of one of the following techniques:                Creating a single controlled clock-domain covering the physical location of both logic sections;        Creating two controlled clock-domains with a known controlled phase relationship, and utilizing a known synchronization technique; and        Creating two phase-independent clock-domains and utilizing a known synchronization technique incorporating a synchronization FIFO. Essentially the FIFO allows the data being transferred to be buffered until the transmitting domain indicates to the receiving domain via the synchronization technique that the buffered data is ready. A disadvantage with the FIFO approach is that it results in a non-deterministic output data pattern.        
The first two techniques may prove strenuous or impractical in some cases, while the third is hampered by the non-deterministic output data pattern. A deterministic data output pattern is required inter alia for chip testing. A chip, or arrangement of chips, that does not produce a deterministic output pattern can be difficult to test.
Examples of prior art include the following US patents and applications: U.S. Pat. No. 6,118,835, Apparatus and method of synchronizing two logic blocks operating at different rates, U.S. Pat. No. 5,905,766, Synchronizer, method and system for transferring data, U.S. Pat. No. 5,537,557, Interface between unsynchronized devices, U.S. Pat. No. 4,949,361 Digital data transfer synchronization circuit and method, U.S. Pat. No. 6,088,412 Elastic buffer to interface digital systems, U.S. Pat. No. 6,075,831 FIFO and system synchronization system and method, U.S. Pat. No. 5,905,766 Synchronizer, method and system for transferring data, U.S. Pat. No. 4,054,744 Data buffer, US-A 2003/0081713 Clock domain crossing FIFO, and US-A 2002/0176512 data transfer device.
There is thus a widely recognized need for, and it would be highly advantageous to have, a technique for data transfer between two relatively distant domains which overcomes the problem of an undetermined, possibly variable phase difference in the synchronization of the domains.